1. Field of the Invention
The present invention relates to a method of fabricating a field effect transistor (FET) with a fin structure, and, particularly, to a method of fabricating a FET with a fin structure through forming a gate structure using a step similar to a damascene process.
2. Description of the Prior Art
With the trend in the industry being towards scaling down the size of metal oxide semiconductor transistors (MOS), three-dimensional or non-planar transistor technology, such as fin field effect transistor technology (Fin-FET) has been developed to replace planar MOS transistors. The three-dimensional structure of a fin-FET increases the overlapping area between the gate and the fin structure of the silicon substrate, and accordingly, the channel region is more effectively controlled. The short channel effect which miniaturized devices may encounter is therefore reduced. The channel region is also wider under the same gate length, and thus the current between the source and the drain is increased.
Since the fin-FET devices have the aforesaid advantages, there is still a need for novel fin-FET devices and methods of fabricating the same to improve performance.